1. Field of the Invention
This invention relates to digital computer systems. More specifically, it relates to digital computer systems having subsystems for regulating the effective processing rate of the central processing unit (CPU).
2. Description of the Prior Art
Certain application programs exist that require a known processing rate to execute in an optimal fashion. For example, a tutorial utilizes software timing loops to sequence images or text across the display of a digital computer system. With the advent of much higher clock speeds for a given processor, and high performance cache memory subsystems, existing techniques for regulating processing rates are not adequate. In the past, in the faster machines, the prior art method of handling the problem has been to provide a "compatibility speed" that forces a high-speed computer (20 Mhz+) to run at a slower speed to emulate a 6 Mhz to 8 Mhz computer. The frequency switch is handled, in most cases, in real time by writing a data value to an I/O port to select a frequency through a multiplexer. The weaknesses in this implementation are the requirement for multiple oscillators, extra circuitry to perform a smooth transition between the two frequencies, and a CPU that has a minimum operating frequency that is lower than the "compatibility" frequency. An additional weakness is that it requires the CPU to be able to dynamically change clock frequencies. Future computer systems may implement internal clocking schemes based on phase locked loops that preclude rapid dynamic change in clocking frequencies because of the inability of the input and output circuits to respond in a timely fashion.
Another prior art system is the insertion of wait states into the main memory subsystem. This technique essentially slows the processing rate of the system by forcing the CPU to artifically wait for memory cycles to complete. This system has the disadvantage of abbreviating the addresses and decoding of addresses at the beginning of the cycle. Also, when the system includes a local cache memory, the cache may contain the particular instruction loop in which event, the insertion of wait states would be ineffective.
Still another prior art method is regulating the processing rate through band width modulation of the system bus. This technique may be used to provide the reduced processing rate by using up time during which the processor must wait. This can be done by extending memory refresh cycles or by providing another "master" that cycles the available bus time between "available" and "busy." The ratio of "available" time to "busy" time multiplied by the relative speed factor of the processor can be derived to yield the effective processing rate desired. However, this system will not perform the desired function in concurrent bus architecture systems that include a local cache memory. In such a system, having the bus in a "busy" state does not preclude the processing of code already contained in the cache memory.